Advanced Packaging & The Chiplet Era: CoWoS, 3D Stacking, and Interposers
How breaking the reticle ceiling reshaped computing: TSMC CoWoS-L, silicon interposers, High Bandwidth Memory (HBM), and 10 TB/s chiplet interconnects.
Read Post →AI LEADER • VISUAL DESIGN ENTHUSIAST
A software engineer with a balanced left and right brain, specializing in pipeline development, DevOps, graphics tools, and site reliability.
How breaking the reticle ceiling reshaped computing: TSMC CoWoS-L, silicon interposers, High Bandwidth Memory (HBM), and 10 TB/s chiplet interconnects.
Read Post →Demystifying GPU execution mechanics: 32-thread lockstep warps, zero-overhead hardware schedulers, the branch divergence penalty, and Little's Law latency hiding.
Read Post →Deconstructing Moonshot AI's Kimi K3.1 Pro: 2.8T MoE with 104B active params, 69 KDA + 24 Gated DSA attention layers, 1M context, MoonViT-V2, and quickstart guide.
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