AI LEADER • VISUAL DESIGN ENTHUSIAST
A software engineer with a balanced left and right brain, specializing in pipeline development, DevOps, graphics tools, and site reliability.
Deconstructing modern GPU silicon hierarchy: GPCs, TPCs, Streaming Multiprocessors, 4-sub-core execution datapaths (FP32/INT32/SFU/TMA), AMD Compute Units, and on-chip SRAM tiers.
Read Post →Beyond the GPU: An architectural deep-dive into Google TPUs, Edge NPUs, and Spatial ASICs—contrasting systolic arrays, deterministic SRAM, and sub-5W silicon.
Read Post →Demystifying the parallel compute revolution: latency vs throughput silicon philosophies, the shift from fixed 3D rasterization to CUDA, and why GPUs power modern AI.
Read Post →
